Fault-Tolerant Data Transfer in a Multiprocessor System by Forward and Backward Hardware Error Recovery

A MIMD processor system is described, which allows forward and backward hardware error recovery (FHER and BHER) for data transfers. Fault-tolerant operation is provided by a multiple bus system and distributed error correction controller (ECC) hardware. Addresses and data are transferred through the bus system together with an error correction code, which is generated and checked by the ECC hardware. FHER is possible for all single-bit errors. Overlapping bus protocols allow these distributed ECC operations to be executed and synchronised concurrently with the transfer. Double-bit and multi-bit transfer errors as well as arbitration errors in the multiple bus system are detected and corrected by automatic rerouteing of the transfer path (BHER). These features improve the reliability of large multiprocessor systems significantly.